DFT Manager

Printed Circuit Board using through-hole technology has excellent physical access for an ICT test fixture. With the dramatic increase in device density on PCBs such a configuration is no longer true. It is increasingly difficult to access with ICT nail each of the nets for structural test purpose. To tackle this problem, DFT Manager tool helps identify the nets on boards that require ICT access. It also helps to optimize the placement of physical access points on boards that have a mix of conventional and Boundary-Scan (JTAG) technology.

In most of the design cycle strategies, ICT access is chosen after the layout phase according to classic constraints such as pad sizes, via diameter, tracking, etc. Where ICT access cannot be defined according to those constraints, the net is classified as ICT-inaccessible.

For today's PCBs, this method of determining ICT access without any relationship to the fault coverage is not sufficient. The use of purely geometrical criteria is at least strange and not adequate with testing challenge the electronic industry now has to offer.

The DFT Manager tool offers an alternative and a better solution to define ICT access criteria. It provides a full and structured approach from schematic capture to final PCB layout.

On boards with JTAG capability, it is usually possible to test some nets of the board for production faults without ICT access to every net on the board. A JTAG interconnect test detects production faults on all pure JTAG nets (nets on which every device lead is scannable) without ICT. To conserve ICT tester channels and to reduce fixturing costs, you can put fixture nails only on those nets that really need them. If the test engineer is entering in a dialog mode with the DFT Manager tool, even more ICT pads can be removed.