Design-For-Testability (DFT) techniques are design efforts specifically employed to ensure that an IC, board or system are testable, as well as suitable for many kinds of the on-board and the on-system activity (CPLD and FPGA configuration, Flash programming, etc). Today, design and testing are no longer separate issues. The emphasis on the quality of the shipped products, coupled with the growing complexity of board designs, requires testing issues to be considered early in the design process so that the design can be modified to simplify the testing and on-board activity processes.

Our DFT comprehensive test coverage reports describe the defect coverage present and recommend how DFT coverage might be optimized to improve yields and reduce cost before the board layout!

DFT is one of the most cost-effective ways of tackling your test problems. We working (consulting, service, training and support) with your:

• managers - to develop DFT guidelines,

• designers - to provide on-the-job DFT consulting,

• test engineers - to help evaluate and implement testability requirements,

• designers, test and production engineers - to develop Boundary-Scan (JTAG) test programs (Interconnect test, SRAM/DRAM test), CPLD and FPGA configuration, Flash programming, I2C programming, etc.