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The JTAG test development services, provided by StarTest, streamline the design and generation of Boundary-Scan tests and in-system programming (ISP) routines on all existent ATPG platforms:
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ScanPlus and ScanExpress of Corelis
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onTAP of Flynn
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ProVision of JTAG Technology
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ScanWorks of Asset InterTech
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CASCON of Goepel
StarTest offers a range of JTAG test development services so that a customer can maintain a high level of cost efficiency by selecting the appropriate JTAG test platform needed for each design.
StarTest supports the customer with services beginning on the early design stages and continuing through assembly and manufacturing. The customer achieves a high return on its investment in JTAG tests and programming routines because StarTest ensures a maximum level of test support throughout the development and manufacturing processes.
We have expertise with the following Boundary-Scan standards:
- JTAG/IEEE 1149.1
Boundary-Scan (digital)
- IEEE 1149.4
Mixed Signal Boundary-Scan (analog)
- IEEE 1149.6
LVDS and Advanced Boundary-Scan
- IEEE 1500 SOC
SOC Embedded Core Test
Some of our JTAG test development services are as following:
- Board-level interconnection test
- Memory cluster test (SSRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, I2C, EEPROM, etc.)
- Multi-board and simultaneous test
- CPLD / FPGA on-board programming, Flash programming
- Cluster test for non-JTAG and analog schematics parts
- Field and production facility service
JTAG Test Coverage Details on Different Platforms
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