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New IEEE 1149.7 Test & Debug Standard Expands and Improves JTAG Functionality

PISCATAWAY, N.J., USA, February 10, 2010 — IEEE, the world's leading professional association for the advancement of technology, today announced the ratification of IEEE 1149.7™ test and debug standard. The new standard expands and improves upon IEEE 1149.1 (JTAG) functionality and is designed to maximize space and cost-savings while maintaining previously made industry investments.

While JTAG has been in use for over 20 years, and will probably continue to be used far into the foreseeable future, the recently released standard IEEE 1149.7 (Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture) has been created to improve upon it and extend its capabilities. The goal was not to replace IEEE standard 1149.1 but to create a complementary standard that addresses the recent changes in the integrated circuit technology and topology. The new standard builds on the existing one in order to implement additional functionality and maximize debug performance while simultaneously maintaining backwards compatibility.

The new IEEE 1149.7 standard (cJTAG or Compact JTAG) provides several major benefits to both board designers and embedded engineers.


Summary of major new features:

 
  • Reduced pin count;
  • Star topology;
  • Individual device addressing;
  • Chip level bypass;
  • Additional power management features.

Summary of major benefits:

 
  • Simplified connections between devices;
  • Improved support for devices with multiple cores;
  • Increased debug performance.




 
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