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ICT Test Development

StarTest™ provides turn-key test program development services for the Teradyne Z18xx family of In-Circuit Testers. Our team of experienced test engineers provides ICT test programs with highest fault coverage and fast cycle time. Our test engineers have successfully completed dozens of the In-Circuit test projects for a broad range of customers and industries. Meeting our customerӳ expectation and on-time delivery of each project has been the basis of our services.


Our ICT Services

 
  • Design-For-Testability (DFT) Analysis.
  • CAD Project Translation.
  • ICT Library Model Development.
  • Standard ICT Test Program Development.
  • User-oriented ICT Test Program Development.
  • CPLD and FLASH Devices On-board Programming.
  • On-the-Facility Program Installation & Support.

Standard Z18xx Test Program Development

The standard Z18xx ICT test programs are cost effective and offer a fast turnaround. This service is most suitable for customers with standard technologies or limited time and budget.

 
  • CAD Translation to Generate Board xy Files.
  • Short and Open Test.
  • Analog Discrete Component Test.
  • Standard Digital Library Test.
  • DeltaScan, WaveScan, and FrameScan Test for Devices that arenӴ in the Library.
  • Program Generation.
  • ICT Fixture Design and Debug (fabrication via subcontractor).
  • Fault Coverage Reports (Device, Pin and Test Oriented).
  • Test Program and ICT Fixture Complete Documentation.

Teradyne Z18xx Testers


On-board Programming of CPLD and FLASH devices

The CPLD devices (Altera, Lattice, Xilinx, etc.) on-board (in-circuit) programming or configuration using STAPL (JBC), or Serial Vector Format (SVF), or VME files and external DOS programs for executing these files. Virtual execution is controlled by the test program.

The FLASH devices on-board programming using Digital Functional Processor (DFP).


User-oriented Z1800 Test Program Development

The user-oriented or advanced Z18xx ICT test programs are designed for complex boards and for customers that require the maximum fault coverage possible at the ICT stage. These programs include all the steps listed in the standard service as well as the following steps (if applicable):

  • Advanced Boundary-Scan;
  • Model Templates Development;
  • Test Vector and Grey Code Development;
  • Digital Cluster Tests;
  • DeltaScan, WaveScan and FrameScan;
  • LED Color & Intensity Check;
  • Single Stage ICT & Functional Test.

Complex ICT jig with bilateral access.

Board under test.

Bottom access wiring.

Top access wiring (1).

Top access wiring (2).

Bottom nail panel.




 
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